Class Code for PCI(e) devices

Class Code
The Class Code register is read-only and is used to identify the
generic function of the device and,in some cases, a specific registerlevel programming interface.

The register is broken into three bytesize fields.
The upper byte (at offset 0Bh) is a base class code which
broadly classifies the type of function the device performs.
The middle byte (at offset 0Ah) is a sub-class code which identifies more
specifically the function of the device.
The lower byte (at offset 09h) identifies a specific register-level programming interface (if any) so that device independent software can interact with the device.


Base Class (at offset 0Bh), Sub-class (at offset 0Ah).

BaseClass = 0x01 - Mass storage controller
            0x02 - Network controller
            0x03 - Display controller
            0x06 - Bridge device
            0x0C - Serial bus controller

Intel x86 系统的中断


支持 256 种向量中断, 从 0~255 编号,可分类为: 异常(exception) 和 中断(interrupt)

1 异常可以分为: Fault, Trap, and Abort, 不使用中断控制器,又不能被屏蔽。
  Intel x86 处理器发布了大约20 种异常.
2 中断可以分为: 非可屏蔽中断 NMI 和 可屏蔽中断 INTR.
3 IRQ 与 中断向量的关系: IRQn 的缺省向量是 n+32.

中断向量表也改叫做中断描述符表IDT(Interrupt Descriptor Table)。